Course Description:
This course contains the introductory part of combinational Logic along with the clear concepts of K-Maps and Quine- Mc Cluskey Method. It also introduces sequential networks with flip flops and FSM. Another concept includes FPGA and VHDL and also testing and verification.
Course Objectives:
The course objective is to provide ample knowledge on digital design process and to enhance the knowledge of hardware design in real scenarios.
Course Contents
Unit 1 (5 Hrs.)
Introduction of logic design, Digital System and Integration, Electronic Design Automation, IC Manufacturing, Logic Families, IC Design Techniques, IC characteristics: fan-out, power dissipation, propagation delay, and noise margin of TTL and CMOS integrated circuit logic devices
Unit 2 (4 Hrs.)
Review of Boolean Algebra and Combinational Logic, Canonical Form, Shannon’s Expansion, Minterms, Maxterms, Prime Implication
Unit 3 (5 Hrs.)
Combinational Network Design: K – Map, Synthesis and Minimization with K – Maps (AND – OR, OR-AND, NAND-NAND, NOR-NOR), Standard Combinational Networks
Unit 4 (7 Hrs.)
Quine- Mc Cluskey Method, Minimization of Boolean expression with Quine-Mc Cluskey method, PROMs and EPROMs, Programmable Array Logic (PAL), Programmed Logic Array (PLA), Gate Arrays, Programmable Gate Array, Full Custom Design
Unit 5 (8 Hrs.)
Sequential Networks: Transition from combinational to sequential network, Direct command flip flop, Initialization of sequential network, Level Enabled Flip-Flops, Synchronization of sequential networks, Edge-triggered Flip Flops, Synchronous and Asynchronous Signals
Unit 6 (6 Hrs.)
Sequential Networks as Finite State Machines: Standard Models, Realization with ASM Diagrams, Synthesis of Synchronous FSM, Time Behavior of Synchronous FSM, Design of input forming, Logic and Output Forming Logic of state machine.
Unit 7 (4 Hrs.)
Field Programmable Gate Arrays (FPGA), VHDL and its use in programmable logic devices (PLDs) like FPGA
Unit 8 (6 Hrs.)
Testing and Verification, Testing Logic Circuits, Combinational gate testing, Combinational network testing, Sequential Testing, Test vector generation, fault, fault model and fault detection, SA0, SA1, Design for Testability
Laboratory Works:
Laboratory Exercise should cover the implementation of combinational and sequential circuits, FSM, FPGA and VHDL. Testing and verification of circuits.
Project Work:
Design a sample of tool kit by using the design concepts of the course.
Reference Books:
- Giuliano Donzellini, Luca Oneto, Domenico Ponta, Davide Anguita, Introduction to Digital System Design, Springer
- Wolf, Wayne, Modern VLSI Design-System on Silicon, Third Edition, Pearson
- Comer, David J. Digital Logic State Machine Design, Third Edition, Oxford University Press
- Ashenden, Peter J, The Student’s Guide to VHDL, Morgan Kaufman