Digital Logic
Full Marks: 60
Pass Marks: 24
Time: 3 hours
Design the sequential circuit with respect to the following state diagram using T flip flops.
Implement F = ∑(0,1,4,5,7) using
Differentiate between combinational circuit and sequential circuit. Design mod-10 synchronous counter using J-K flip-flop. Show necessary truth tables and K-maps.